This application incorporates by reference of Taiwan application Serial No. 090126329, filed on Oct. 24, 2001.
1. Field of the Invention
The invention relates in general to a phase locked loop, and more particularly to phase locked loop with high operating speed.
2. Description of the Related Art
Phase locked loop (PLL) is a circuit for controlling the frequency and the phase of its output signal according to a criterion. Nowadays, it has been wildly used in the wireless communications. For example, the PLL is used to provide the clock signal in the decoding process after the receiver receives a data signal. The frequency and the phase of the clock signal play an important role of success decoding of the data signal. If the initial phase error between the data signal and the clock signal is too large, it will cost about several microseconds to be in the phase locked state. Only when the phase error between the data signal and the clock signal decreases rapidly, can the decoding of the data signal succeed efficiently. To speed the PLL to go to the phase locked state, the phase of the clock signal can be first adjusted to decrease the phase error between the data signal and the clock signal by applying a voltage controlled oscillator (VCO) and a multi-phase generator (MPG).
FIG. 1 illustrates the block diagram of a PLL 100 according to a traditional method, wherein the PLL 100 is used to receive the data signal DATA. After the data signal DATA passes through the inverter 102(1) and inverter 102(2), a data signal DATAX is produced. Then, the phase detector 104 receives the data signal DATAX and a clock signal CLKX, and outputs a rising signal UP and a descending signal DN to a charge pump 106 according to the phase error between the data signal DATAX and the clock signal CLKX. The charge pump 106 outputs a charge current Icp to a loop filter 108 according to the pulse width between the rising signal UP and the descending signal DN. The loop filter 108 filters out the high frequency part of the charge current Icp and outputs a voltage V.
The VCO and MPG 110 receives the voltage V and then outputs some phase clock signals, for example six phase clock signal: P0xcx9cP5. They have same frequency, which corresponds to the voltages V, but are regularly out of phase. The phase clock signal P1 lags the phase clock signal P0 by a phase delay of 60 degree, being 360/6, and the phase clock signal P2 also lags the phase clock signal P1 by a phase delay of 60 degree, and so on.
All the phase clock signals P0xcx9cP5 are inputted to a phase selector 112, and one of the phase clock signals P0xcx9cP5 is selected as the basic clock signal PCLK and is outputted from the phase selector 112 according to the selecting signal PSEL. Then, the basic clock signal PCLK is inputted to a logic circuit unit 114 and a clock signal CLK is outputted there from, wherein the logic circuit unit 114 can be a divider or other logic circuit capable of processing the basic clock signal PCLK. Afterwards, the clock signal CLK is processed orderly by two inverters 103(1), 103(2), and the clock signal CLKX is produced from the inverter 103(2). The clock signal CLKX has a delay time Td to the phase clock signal P0xcx9cP5, wherein the delay time Td comprises the delay time of the phase selector 112, logic circuit unit 114, and two inverters 103(1), 103(2).
Therefore, the phase clock signals P0xcx9cP5 with the most proper phase is selected as the basic clock signal PCLK by comparing the data signal DATAX with the phase clock signals P0xcx9cP5 having a dummy delay Td. As shown in FIG. 1, the phase clock signal P0xcx9cP5 are respectively inputted into a first delay units 120(0)xcx9c120(5), a second delay units 122(0)xcx9c122(5), the inverters 124(0)xcx9c124(5), and the inverters 125(0)xcx9c125(5). The delay time of the first delay unit 120 and the second delay unit 122 are respectively the same with that of the phase selector 112 and the logic circuit 114. The total delay time of the first delay units 120, the second delay units 122, the inverters 124, and the inverters 125 is the dummy delay Td. Thus, the dummy-delay phase clock signal PX0xcx9cPX5, being the phase clock signals P0xcx9cP5 having the dummy delay Td, are obtained.
After the dummy-delay phase clock signal PX0xcx9cPX5 are produced, they are inputted into a transition detector 118, as well as the data signal DATAX. The transition detector 118 detects the dummy-delay phase clock signal PX0xcx9cPX5 with the closest phase, compared with the data signal DATAX, and then outputs a corresponding clock period value CLKP. An optimal phase encoder 116 receives the clock period value CLKP and outputs a phase select signal PSEL to the phase selector 112. Finally, according to the clock period value CLKP, the phase selector 112 selects the most proper phase clock signal P0xcx9cP5 so as to make the clock signal CLKX have the closest phase with data signal DATAX. Therefore, the rapid phase locked is achieved by properly choosing the phase clock signal P0xcx9cP5.
However, each of the first delay units 120(0)xcx9c120(5) usually has different delay time, as well as the second delay units 122(0)xcx9c122(5), the inverters 124(0)xcx9c124(5), and the inverters 125(0)xcx9c125(5), which is resulted from the process variation of fabrication manufacturing and the lines difference of layout. Therefore, the dummy-delay phase clock signals PX0xcx9cPX5 are different in phase spacing. For example, when the delay time of the dummy-delay phase clock signal PX0 to the phase clock signal P0 is larger than that of the dummy-delay phase clock signal PX1 to the phase clock signal P1, the phase spacing between the dummy-delay phase clock signal PX0 and dummy-delay phase clock signal PX1 is larger than 60 degree. Thus, other phase spacings among the dummy-delay phase clock signal PX0xcx9cPX5 will be unequal, too. Upon the same delay time, a larger phase error and more apparent phenomenon of the unequal phase spacing will be particularly produced as the high-frequency signal is processed, compared with the low-frequency signal. Hence, the operation speed and the resolution of the PLL will be lowered largely.
It is therefore an object of the invention to provide a phase locked loop (PLL) with high operating speed and high resolution, particularly in the processing of high frequency.
The PLL, receiving a data signal and generating a clock signal, comprises a phase detector, a loop filter, a voltage controlled oscillator (VCO) and multi-phase generator (MPG), a transition detector, an optimal phase encoder, and a phase selector is disclosed. The phase detector is used for receiving the data signal and the clock signal, and for outputting a phase difference signal according to the phase difference between the data signal and the clock signal. The loop filter is used for outputting a voltage according to the phase difference signal. The voltage controlled oscillator (VCO) and multi-phase generator (MPG) is used for outputting N phase clock signals, wherein (i+1)th phase clock signal lags ith phase clock signal by a phase delay, and all of the N phase clock signals have same frequency corresponding to the voltage. The N and the i are integers and have a relationship of 0xe2x89xa6i less than Nxe2x88x921. The transition detector is used for outputting a data period value and a clock period value by receiving the N phase clock signals, the data signal and the clock signal, wherein the period between the level transition of ith phase clock signal and that of (i+1)th phase clock signal is defined as ith transition region, and the data period value and the clock period value are respectively the numbers of the transition regions in which the level transitions of the data signal and the clock signal occur. The optimal phase encoder is used for outputting a phase select signal according to the data period value and the clock period value, wherein the phase select signal corresponds to the difference between the clock period value and the data period value. The phase selector is used for outputting a jth phase clock signal according to the phase select signal, wherein the jth phase clock signal corresponds to the clock signal, and the j is an integer and obeys a relationship of 0xe2x89xa6j less than Nxe2x88x921.
Alternatively, the PLL, receiving a data signal and generating a clock signal, can also comprise a phase detector, a loop filter, a VCO and MPG, an optimal phase determination unit, and a phase selector. The phase detector is used for receiving the data signal and the clock signal, and for outputting a phase difference signal according to the phase difference between the data signal and the clock signal. The loop filter is used for outputting a voltage according to the phase difference signal. The voltage VCO and MPG is used for outputting N phase clock signals, wherein (i+1)th phase clock signal lags ith phase clock signal by phase delay, and all of the N phase clock signals have same frequency corresponding to the voltage. The N and the i are integers and have a relationship of 0xe2x89xa6ixe2x88x921. The optimal phase determination unit is used for outputting a phase select signal by receiving the N phase clock signals, the data signal, and the clock signal, wherein the phase difference between the data signal and the clock signal corresponds to m transition regions, said m is an integer and obeys the relation 0xe2x89xa6m less than N. The phase selector is used for outputting a jth phase clock signal according to the phase select signal, wherein the jth phase clock signal corresponds to the clock signal, and the j is an integer and obeys a relationship of 0xe2x89xa6j less than Nxe2x88x921.